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| PRELIMINARY Integrated Circuit Systems, Inc. ICS844071I FEMTOCLOCKSTM CRYSTAL-TO- LVDS CLOCK GENERATOR FEATURES * (1) Differential LVDS output * Crystal oscillator interface, 18pF parallel resonant crystal (20.833MHz - 28.3MHz) * Output frequency range: 62.5MHz - 170MHz * VCO range: 500MHz - 680MHz * RMS phase jitter @ 150MHz, using a 25MHz crystal (12kHz - 20MHz): 0.75ps (typical) * 3.3V or 2.5V operating supply * -40C to 85C ambient operating temperature * Replaces ICS844051-11 GENERAL DESCRIPTION The ICS844071I is a Serial ATA (SATA)/Serial Attached SCSI (SAS) Clock Generator and a HiPerClockSTM member of the HiPerClocks TM family of high performance devices from ICS. The ICS844071I uses an 18pF parallel resonant crystal over the range of 20.833MHz - 28.3MHz. For SATA/SAS applications, a 25MHz crystal is used and either 75MHz or 150MHz may be selected with the FREQ_SEL pin. The ICS844071I has excellent <1ps phase jitter performance, over the 12kHz 20MHz integration range. The ICS844071I is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. ICS COMMON CONFIGURATION TABLE Inputs Crystal Frequency (MHz) 25 25 26.041666 26.041666 26.5625 26.5625 FREQ_SEL 0 1 0 1 0 1 M 24 24 24 24 24 24 N 4 8 4 8 4 8 Multiplication Value M/N 6 3 6 3 6 3 Output Frequency (MHz) 150 75 156.25 78.125 159.375 79.675 BLOCK DIAGRAM FREQ_SEL Pullup PIN ASSIGNMENT FREQ_SEL N 0 /4 1 /8 VDDA GND XTAL_OUT XTAL_IN 1 2 3 4 8 7 6 5 VDD Q nQ FREQ_SEL XTAL_IN OSC XTAL_OUT Phase Detector VCO 500MHz - 680MHz Q nQ ICS844071I 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View M = /24 (fixed) The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 844071AGI www.icst.com/products/hiperclocks.html REV. A JULY 13, 2005 1 PRELIMINARY Integrated Circuit Systems, Inc. ICS844071I FEMTOCLOCKSTM CRYSTAL-TO- LVDS CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number 1 2 3, 4 5 6, 7 8 Name VDDA GND XTAL_OUT, XTAL_IN FREQ_SEL nQ, Q VDD Power Power Input Input Output Power Pullup Type Description Analog supply pin. Power supply ground. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Frequency select pin. LVCMOS/LVTTL interface levels. Differential clock outputs. HSTL interface levels. Core supply pin. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol CIN RPULLUP Parameter Input Capacitance Input Pullup Resistor Test Conditions Minimum Typical 4 51 Maximum Units pF k 844071AGI www.icst.com/products/hiperclocks.html 2 REV. A JULY 13, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844071I FEMTOCLOCKSTM CRYSTAL-TO- LVDS CLOCK GENERATOR 4.6V -0.5V to VDD + 0.5 V 10mA 15mA 101.7C/W (0 mps) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD Inputs, VI Outputs, IO (LVDS) Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = -40C TO 85C Symbol VDD VDDA IDD IDDA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 TBD TBD Maximum 3.465 3.465 Units V V mA mA TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 2.5V5%, TA = -40C TO 85C Symbol VDD VDDA IDD IDDA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 2.375 2.375 Typical 2.5 2.5 TBD TBD Maximum 2.625 2.625 Units V V mA mA TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V5% OR 2.5V5%, TA = -40C TO 85C Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current FREQ_SEL FREQ_SEL Test Conditions VDD = 3.3V VDD = 2.5V VDD = 3.3V VDD = 2.5V VDD = VIN = 3.465V or 2.625V VDD = 3.465V or 2.625V, VIN = 0V -150 Minimum 2 1.7 -0.3 -0.3 Typical Maximum VDD + 0.3 VDD + 0.3 0.8 0.7 5 Units V V V V A A NOTE 1: Outputs terminated with 50 to VDD/2. See Parameter Measurement Information Section, "3.3V Output Load Test Circuit". 844071AGI www.icst.com/products/hiperclocks.html 3 REV. A JULY 13, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844071I FEMTOCLOCKSTM CRYSTAL-TO- LVDS CLOCK GENERATOR Minimum Typical 350 40 1.25 50 Maximum Units mV mV V mV TABLE 3D. LVDS DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = -40C TO 85C Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change Test Conditions TABLE 3E. LVDS DC CHARACTERISTICS, VDD = VDDA = 2.5V5%, TA = -40C TO 85C Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change Test Conditions Minimum Typical 350 50 1.2 40 Maximum Units mV mV V mV TABLE 4. CRYSTAL CHARACTERISTICS Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level 20.833 Test Conditions Minimum Typical Fundamental 28.3 50 7 1 MHz pF mW Maximum Units TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = -40C TO 85C Symbol fOUT Parameter Output Frequency RMS Phase Jitter ( Random); NOTE 1 Output Rise/Fall Time 150MHz @ Integration Range: 12kHz - 20MHz 75MHz @ Integration Range: 12kHz - 20MHzz 20% to 80% Test Conditions Minimum 62.5 0.75 0.68 300 50 Typical Maximum 170 Units MHz ps ps ps % tjit(O) tR / tF odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plots following this section. TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 2.5V5%, TA = -40C TO 85C Symbol fOUT Parameter Output Frequency RMS Phase Jitter ( Random); NOTE 1 Output Rise/Fall Time 150MHz @ Integration Range: 12kHz - 20MHz 75MHz @ Integration Range: 12kHz - 20MHzz 20% to 80% Test Conditions Minimum 62.5 0.96 0.98 300 50 Typical Maximum 170 Units MHz ps ps ps % tjit(O) tR / tF odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plots following this section. 844071AGI www.icst.com/products/hiperclocks.html 4 REV. A JULY 13, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844071I FEMTOCLOCKSTM CRYSTAL-TO- LVDS CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION Qx 3.3V5% POWER SUPPLY SCOPE 2.5V5% POWER SUPPLY Qx + Float GND - SCOPE + Float GND - LVDS nQx LVDS nQx LVDS 3.3V OUTPUT LOAD AC TEST CIRCUIT 80% Clock Outputs 80% VSW I N G 20% tR tF 20% LVDS 2.5V OUTPUT LOAD AC TEST CIRCUIT nQ Q t PW t PERIOD odc = t PW t PERIOD x 100% OUTPUT RISE/FALL TIME Phase Noise Plot Noise Power OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD VDD DD out Phase Noise Mask DC Input LVDS out VOS/ VOS f1 Offset Frequency f2 RMS Jitter = Area Under the Masked Phase Noise Plot RMS PHASE JITTER VDD VDD OFFSET VOLTAGE SETUP out DC Input LVDS 100 VOD/ VOD out REV. A JULY 13, 2005 DIFFERENTIAL OUTPUT VOLTAGE SETUP 844071AGI www.icst.com/products/hiperclocks.html 5 PRELIMINARY Integrated Circuit Systems, Inc. ICS844071I FEMTOCLOCKSTM CRYSTAL-TO- LVDS CLOCK GENERATOR APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS844071I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA pin. 3.3V or 2.5V VDD .01F VDDA .01F 10F 10 FIGURE 1. POWER SUPPLY FILTERING RECOMMENDATIONS FOR UNUSED INPUT INPUTS: AND OUTPUT PINS OUTPUTS: LVCMOS OUTPUT: All unused LVCMOS output can be left floating. We recommend that there is no trace attached. LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVHSTL OUTPUT All unused LVHSTL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVDS OUTPUT All unused LVDS outputs should be terminated with 100 resister between the differential pair. LVDS - Like OUTPUT All unused LVDS outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. HCSL OUTPUT All unused HCSL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. SSTL OUTPUT All unused SSTL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. REV. A JULY 13, 2005 CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resister can be tied from XTAL_IN to ground. CLK INPUT: For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1k resister can be tied from the CLK input to ground. TEST_CLK INPUT: For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1k resister can be tied from the TEST_CLK to ground. CLK/nCLK INPUT: For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resister can be tied from CLK to ground. PCLK/nPCLK INPUT: For applications not requiring the use of a differential input, both the PCLK and nPCLK pins can be left floating. Though not required, but for additional protection, a 1k resister can be tied from PCLK to ground. SELECT PINS: All select pins have internal pull-ups and pull-downs; additional resistance is not required but can be added for additional protection. A 1k resister can be used. 844071AGI www.icst.com/products/hiperclocks.html 6 PRELIMINARY Integrated Circuit Systems, Inc. ICS844071I FEMTOCLOCKSTM CRYSTAL-TO- LVDS CLOCK GENERATOR resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. CRYSTAL INPUT INTERFACE The ICS844071I has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel XTAL_OUT C1 22p X1 18pF Parallel Crystal XTAL_IN C2 33p Figure 2. CRYSTAL INPUt INTERFACE 3.3V, 2.5V LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 3. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the un-used outputs. 2.5V or 3.3V VDD LVDS_Driv er + R1 100 - 100 Ohm Differential Transmission Line FIGURE 3. TYPICAL LVDS DRIVER TERMINATION 844071AGI www.icst.com/products/hiperclocks.html 7 REV. A JULY 13, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844071I FEMTOCLOCKSTM CRYSTAL-TO- LVDS CLOCK GENERATOR RELIABILITY INFORMATION TABLE 6. JAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP JA by Velocity (Meters per Second) 0 Multi-Layer PCB, JEDEC Standard Test Boards 101.7C/W 1 90.5C/W 2.5 89.8C/W TRANSISTOR COUNT The transistor count for ICS844071I is: 2533 844071AGI www.icst.com/products/hiperclocks.html 8 REV. A JULY 13, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844071I FEMTOCLOCKSTM CRYSTAL-TO- LVDS CLOCK GENERATOR 8 LEAD TSSOP PACKAGE OUTLINE - G SUFFIX FOR TABLE 7. PACKAGE DIMENSIONS SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 2.90 6.40 BASIC 4.50 Millimeters Minimum 8 1.20 0.15 1.05 0.30 0.20 3.10 Maximum Reference Document: JEDEC Publication 95, MO-153 844071AGI www.icst.com/products/hiperclocks.html 9 REV. A JULY 13, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844071I FEMTOCLOCKSTM CRYSTAL-TO- LVDS CLOCK GENERATOR Shipping Packaging tube 2500 tape & reel Temperature -40C to 85C -40C to 85C TABLE 8. ORDERING INFORMATION Part/Order Number ICS844071AGI ICS844071AGIT Marking 4071A 4071A Package 8 Lead TSSOP 8 Lead TSSOP The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 844071AGI www.icst.com/products/hiperclocks.html 10 REV. A JULY 13, 2005 |
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